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There are 29 companies in the field of Application Specific Integrated Circuit (ASIC) on spotfolio that produce or deliver products, that utilize or research technologies or that are otherwise engaged in topics such as Power, ASIC, Embedded, Power-Supply, Analog, System, Signal, Design .

Start-ups (2)

Early-stage companies (10)

Established companies (16)

The majority of these companies is located in the following countries.

Canada (10)

United States (5)

China (4)

Germany (2)

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LinearChip

established

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is shown here. MEMS – Driver; timing and control Signal Processing and Control – Sensor signal amplification (low noise; wide dynamic range; chopper ...

ultrasound; measurement Military – Bus Interface (1553; NTDS); radar; infrared; signal processing ATE/Instrumentation – Pin driver; vernier caliper; precision

MSPA1000: Mixed Signal Platform Architecture LinearChip has developed a new ASSP design platform called the MSPA1000 (Mixed Signal Platform Architecture) ...

of thousands of designs in development today. Targeting low cost, mixed signal applications requiring 8 to 32 bit performance, LinearChip has put together ...

selection of OS Test Insertion and Mixed signal test: - Embedded self test methodologies - In house experts in mixed signal test development and testing strategy

Awinic Shanghai awinic technology co.,ltd

established

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Company profile - History & honors - Partners Leading on Analog and Mixed-Signal IC in China Meeting customer needs is awinic's only reason to exist |High-quality ...

company focusing on high-quality and high-performance IC design of Mixed signal, analog, and RF for mobile phone, AI, IoT, automotive electronics, wearables

phone, laptop, NB-IoT, gaming device, etc. Product name Actuator Type Input Signal Max Output Voltage(V) SRAM (kB) Loading(Ω) CLK Boost LRA Calibration Startup

Tusk IC

start-up

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GHz downconverter in 90nm CMOS A 0.54THz signal generator in 40nm CMOS with 22 GHz tuning range A 0.54THz signal generator in 40nm CMOS with 22 GHz tuning ...

range and Integrated Planar Antenna A 0.61THz (top) and 0.57THz (bottom) signal source in 28nm bulk CMOS with integrated antenna for non-destructive testing

Swedish Telecom

established

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that degradation of the laser. Loss of signal (LOS) output is provided to indicate the loss of an input optical signal of receiver or the link status with ...

the module. 3 7 Rate Select No connection required 4 8 LOS Loss of Signal indication. Logic 0 indicates normal operation. 5 9 VEER Receiver Ground ...

and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal. Figure2. Pin out of Connector Block on Host Board II. Absolute Maximum ...

Power Supply Voltage Max. Unit -40 85 ºC HA 5 95 VCC -0.5 4 V Signal Input Voltage -0.3 Vcc+0.3 V Receiver Damage Threshold +5 © Copyright ...

Input Saturation Power (Overload) PSAT -10 dBm Los Of Signal Assert PA -40 dBm Los Of Signal De-assert PD LOS Hysteresis PA-PD Typ. 0.5 Max. ...

@PRBS=2^23-1 NRZ. Note (2): When LOS de-asserted, the RX data+/- output is signal output. VI. Electrical Interface Characteristics Parameter Transmitter

that degradation of the laser. Loss of signal (LOS) output is provided to indicate the loss of an input optical signal of receiver or the link status with ...

the module. 3 7 Rate Select No connection required 4 8 LOS Loss of Signal indication. Logic 0 indicates normal operation. 5 9 VEER Receiver Ground ...

and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal. Figure2. Pin out of Connector Block on Host Board II. Absolute Maximum ...

Power Supply Voltage Max. Unit -40 85 ºC HA 5 95 VCC -0.5 4 V Signal Input Voltage -0.3 Vcc+0.3 V Receiver Damage Threshold +5 © Copyright ...

Input Saturation Power (Overload) PSAT -10 dBm Los Of Signal Assert PA -40 dBm Los Of Signal De-assert PD LOS Hysteresis PA-PD Typ. 0.5 Max. ...

@PRBS=2^23-1 NRZ. Note (2): When LOS de-asserted, the RX data+/- output is signal output. VI. Electrical Interface Characteristics Parameter Transmitter

Efabless

early-stage

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1-pin clock input signal input -0.5 VDD3V3 + 0.3 XI crytal oscillator input signal inout -0.5 VDD3V3 + 0.3 XO crytal oscillator output signal inout -0.5 VDD3V3 ...

input signal input -0.5 VDD3V3 + 0.3 SCK standalone SPI clock signal input -0.5 VDD3V3 + 0.3 CSB standalone SPI chip select (sense inverted) signal input ...

receive channel signal input -0.5 VDD3V3 + 0.3 ser_tx UART transmit channel signal output -0.5 VDD3V3 + 0.3 irq Dedicated external interrupt signal input -0.5 ...

(active low) signal input -0.5 VDD3V3 + 0.3 flash_clk Flash SPI clock signal input -0.5 VDD3V3 + 0.3 flash_io0 Flash SPI channel 0 signal inout -0.5 xAVDD_N ...

channel 0 signal inout -0.5 xAVDD_N + 0.3 flash_io2 Flash SPI channel 0 signal inout -0.5 xAVDD_N + 0.3 flash_io3 Flash SPI channel 0 signal inout -0.5 ...

GPIO channel 15 signal output -0.5 VDD3V3 + 0.3 gpio_14 GPIO channel 14 signal output -0.5 VDD3V3 + 0.3 gpio_13 GPIO channel 13 signal output -0.5 VDD3V3

1-pin clock input signal input -0.5 VDD3V3 + 0.3 XI crytal oscillator input signal inout -0.5 VDD3V3 + 0.3 XO crytal oscillator output signal inout -0.5 VDD3V3 ...

data input signal input -0.5 VDD3V3 + 0.3 SDO housekeeping SPI data output signal output -0.5 VDD3V3 + 0.3 SCK housekeeping SPI clock signal input -0.5 ...

(sense inverted) signal input -0.5 VDD3V3 + 0.3 ser_rx UART receive channel signal input -0.5 VDD3V3 + 0.3 ser_tx UART transmit channel signal output -0.5 VDD3V3 ...

I2C data channel signal inout -0.5 VDD3V3 + 0.3 i2c_scl I2C clock channel signal inout -0.5 VDD3V3 + 0.3 spi_sck SPI master clock signal output -0.5 VDD3V3 ...

master select signal output -0.5 VDD3V3 + 0.3 spi_sdo SPI master data output signal output -0.5 VDD3V3 + 0.3 spi_sdi SPI master data input signal input -0.5 ...

interrupt signal input -0.5 VDD3V3 + 0.3 flash_csb Flash SPI chip select (active low) signal output -0.5 VDD3V3 + 0.3 flash_clk Flash SPI clock signal output

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